Liquid crystal display and display system comprising the same

ABSTRACT

A liquid crystal display and a display system including the same are provided in one or more embodiments. For example, a liquid crystal display may include for an embodiment a bi-directional channel, a memory in which driving signal generation data including information required to generate a plurality of driving signals and EDID (Extended Display Identification Data) are stored, and a timing controller which receives the driving signal generation data and the EDID from the memory and transmits the EDID to the outside through the bi-directional channel. The driving signal generation data and the EDID may be transmitted from the memory to the timing controller via a single interface. A first time period during which the driving signal generation data is transmitted may not overlap with a second time period during which the EDID is transmitted.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2008-0092259 filed on Sep. 19, 2008 in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein byreference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates generally to a liquid crystal display anda display system comprising the same.

2. Related Art

A liquid crystal display typically includes a liquid crystal panelhaving a first substrate with a pixel electrode, a second substrate witha common electrode, and a dielectric, anisotropic liquid crystal layerinterposed between the first substrate and the second substrate. Anelectric field is generated between the pixel electrode and the commonelectrode, and the intensity of the electric field is adjusted tocontrol an amount of light transmitted through the liquid crystal,thereby displaying desired images on the liquid crystal panel. Since theliquid crystal display is not self-luminescent, a light source such as abacklight unit is provided in the rear of the liquid crystal panel.

In order to drive the liquid crystal display, the liquid crystal panel,driving integrated circuits (“ICs”), which transmit signals required todisplay an image, the backlight unit, an inverter, a power supplymodule, which provides a power supply voltage required to drive theliquid crystal display, and an external transmission cable, whichtransmits an image signal, must be electrically connected to oneanother.

To electrically connect the functional blocks, an LVDS (Low VoltageDifferential Signaling) interface has widely been used as an internalinterface, and a VGA (Video Graphics Array), a DVI (Digital Video/visualInteractive) and the like, have been widely used as an externalinterface.

In the conventional connection standards, such as LVDS/DVI, EDID(Extended Display Identification Data), information is stored in ascaler board. The EDID information includes information about horizontaland vertical frequencies, a maker identifier, a model identifier of thedisplay device, serial numbers, and so on.

SUMMARY

The present disclosure provides a liquid crystal display having reducedwirings in accordance with one or more embodiments.

The present disclosure also provides a display system having reducedwirings in accordance with one or more embodiments.

The above embodiments and other aspects of the present disclosure willbe described in or be apparent from the following description ofembodiments.

In an embodiment, a liquid crystal display may include a bi-directionalchannel, a memory in which driving signal generation data includinginformation required to generate a plurality of driving signals and EDID(Extended Display Identification Data) are stored, and a timingcontroller. The timing controller may receive the driving signalgeneration data and the EDID from the memory and transmit the EDID tothe outside through the bi-directional channel. The driving signalgeneration data and the EDID may be transmitted from the memory to thetiming controller via a single interface. A first time period duringwhich the driving signal generation data is transmitted may not overlapwith a second time period during which the EDID is transmitted.

In an embodiment, a display system may include a bi-directional channel,a memory in which driving signal generation data for generating aplurality of control signals and EDID (Extended Display IdentificationData) may be stored, a liquid crystal display including a timingcontroller which receives the driving signal generation data and theEDID from the memory and transmits the EDID to the outside through thebi-directional channel, and a host device receiving the EDID from theliquid crystal display. The driving signal generation data and the EDIDmay be transmitted from the memory to the timing controller via a singleinterface. A first time period during which the driving signalgeneration data is transmitted may not overlap with a second time periodduring which the EDID is transmitted.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present disclosurewill become more apparent by describing exemplary embodiments thereofwith reference to the attached drawings in which:

FIG. 1 is a block diagram showing an example liquid crystal display anda display system including the same in accordance with an embodiment;

FIG. 2 is a conceptual diagram illustrating the example liquid crystaldisplay and display system including the same shown in FIG. 1 inaccordance with an embodiment;

FIG. 3 is a cross-sectional view of a transmission cable shown in FIG. 2in accordance with an embodiment;

FIG. 4 is a block diagram showing a memory and a timing controller shownin

FIG. 2 in accordance with an embodiment;

FIG. 5 is a timing diagram illustrating operation of memories of firstand second communication modules shown in FIG. 4 in accordance with anembodiment;

FIG. 6 is a block diagram showing an exemplary liquid crystal displayand a display system including the same in accordance with anembodiment; and

FIG. 7 is a timing diagram illustrating operation of memories of firstand second communication modules shown in FIG. 6 in accordance with anembodiment.

DETAILED DESCRIPTION

Advantages and features of the present disclosure and systems andmethods of accomplishing the same may be understood more readily byreference to the following detailed description of one or moreembodiments and the accompanying drawings. Embodiments of the presentdisclosure may, however, be embodied in many different forms and shouldnot be construed as being limited to the example embodiments set forthherein. Rather, these embodiments are provided so that this disclosurewill be thorough and complete and will fully convey the concept of thedisclosure to those skilled in the art, and the present invention willonly be defined by the appended claims. Like reference numerals refer tolike elements throughout the specification. In the drawings, thethicknesses of layers and regions are exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numbers refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present disclosure.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, one or more embodiments of a liquid crystal display and adisplay system including the same will be described in detail withreference to FIGS. 1 through 5. FIG. 1 is a block diagram showing anexemplary liquid crystal display and a display system including thesame, FIG. 2 is a conceptual diagram for explaining the liquid crystaldisplay and the display system including the same shown in FIG. 1, FIG.3 is a cross-sectional view of a transmission cable shown in FIG. 2,FIG. 4 is a block diagram showing a memory and a timing controller shownin FIG. 2, and FIG. 5 is a timing diagram for explaining memories offirst and second communication modules shown in FIG. 4.

In an exemplary embodiment, the display system 10 may include a liquidcrystal display 200 and a host device 100.

The liquid crystal display 200 may include a bi-directional channel 320,a memory 220 in which driving signal generation data includinginformation required to generate a plurality of driving signals and EDIDare stored, and a timing controller 210. The timing controller 210 mayreceive the driving signal generation data and the EDID from the memory220 and may transmit the EDID to the outside through the bi-directionalchannel 320. The driving signal generation data and the EDID may betransmitted from the memory 220 to the timing controller 210 via asingle interface 270. The time in which the driving signal generationdata is transmitted may not overlap the time in which the EDID istransmitted.

The host device 100 may receive EDID from the liquid crystal display200. The host device 100 may transmit a signal to the liquid crystaldisplay 200. The signal may be a video signal VIDEO and/or an audiosignal AUDIO, that is, one of a video signal VIDEO and an audio signal(AUDIO), or a combination thereof.

The liquid crystal display 200 and the host device 100 may be connectedto a transmission cable 300, and the liquid crystal display 200 maytransmit the EDID through the transmission cable 300 in a DisplayPortinterfacing format.

The transmission cable 300 may include a one-way channel 310 and abi-directional channel 320. For example, when various signals areexchanged between the liquid crystal display 200 and the host device 100through the transmission cable 300 in the DisplayPort interfacingformat, the one-way channel 310 may be a main link, and thebi-directional channel 320 may be an auxiliary channel.

In recent years, a search has been under way for a new standard that canrealize representation of more colors, a higher resolution, and a higherrefresh rate while simplifying electrical connection. The VideoElectronics Standards Association (“VESA”) has put forth at least onesuch new interface standard. One of the new standards is a digitaldisplay interface called ‘DisplayPort’.

DisplayPort is an interface intended to transmit a high-quality videosignal and a high-quality audio signal using a single cable, and mayoffer up to 10.8 Gbps of bandwidth. Optionally, DisplayPort may protectcontent. A new interface such as DisplayPort may not require a scalerboard. Accordingly, a new structure for storing EDID may be desired.

In other words, the liquid crystal display 200 may be connected to thehost device 100 through the transmission cable 300 to receive andtransmit various signals. The liquid crystal display 200 may receive theEDID from the memory 220 and transmit the EDID to the host device 100through the bi-directional channel 320 of the transmission cable 300.That is, the liquid crystal display 200 may receive the driving signalgeneration data from the same memory 220 and transmit the driving signalgeneration data into the timing controller 210. The timing controller210 may receive the driving signal generation data and the EDID from thememory 220 through a single interface 270. The driving signal generationdata and the EDID may be transmitted at different times. The displaysystem 10 may be a portable computer, e.g., a notebook computer.Further, the host device 100 may be a main board of a notebook computer,e.g., a mother board. However, this is only an example, but the presentdisclosure is not limited thereto.

Referring to FIG. 2, the liquid crystal display 201 may include a liquidcrystal panel (not shown), a printed circuit board 260, and internalmodules 510, 520, 530, and 540.

The liquid crystal panel may include a plurality of gate lines (notshown), a plurality of data lines (not shown), and a plurality of pixels(not shown) formed at intersections of the gate lines and the datalines. The liquid crystal panel may display an image in response to avideo data voltage received from a data driver DIC and a gate driver(not shown).

The printed circuit board 260 may include driving integrated circuits(not shown), a first connector 230, a second connector 250, a memory220, and a timing controller 210.

The data driver DIC may be mounted on the printed circuit board 260 andmay generate various signals necessary to drive the liquid crystaldisplay 201. For example, the gate driver (not shown) and the datadriving integrated circuit DIC may be connected to the liquid crystalpanel 100 to supply a gate signal and a video data voltage to displayimages. In FIG. 1, the data driver DIC is connected to the liquidcrystal panel 100 in the form of an integrated circuit, and the gatedriver is mounted on the liquid crystal panel 100. However, the forms ofthe data driver DIC and the gate driver are not limited thereto, and thedata driver DIC and the gate driver may be alternatively mounted on orconnected to the liquid crystal panel 100.

The printed circuit board 260 and the liquid crystal display 201, whichmay include first and second connectors 230 and 250, respectively, mayreceive and transmit various signals from/to external devices (notshown) through the first connector 230. Internal modules may receive andtransmit various signals through the second connector 250.

The first connector 230 may transmit external signals including an imagedata signal VIDEO, an audio data signal AUDIO, and/or a video controlsignal CON_V or an audio control signal CON_A, to the printed circuitboard 260. The first connector 230 may be connected to the transmissioncable 240 transmitting the data signal and/or the control signal whichare output from the external host device (100 of FIG. 1), e.g., a motherboard of a notebook computer. Here, the video control signal CON_V maycontrol luminance of an image, and the audio control signal CON_A maycontrol audio volume. Alternatively, the control signal may be a monitorcontrol command set (“MCCS”) standardized by the Video ElectronicsStandards Association (“VESA”).

The second connector 250 may be connected to the modules of the LCD 201so that the modules can interface with one another through the secondconnector 250. The second connector 250 may allow various modules, forexample, the timing controller 210, the inverter 510, the power supplymodule 520, the handling module 530, and the mode display module 540 tobe connected to one another to be operable.

The memory 220 may store the driving signal generation data and theEDID. The EDID (Extended Display Identification Data) may includevarious kinds of data necessary for the display system to distinguishthe liquid crystal display 200. For example, the EDID may includeinformation about basic display parameters or characteristics, such asthe full resolution of a monitor, horizontal and vertical frequencies,color information, a maximum image size, or a frequency range limit, andinformation about horizontal and vertical frequencies, a makeridentifier, a model identifier, serial numbers, and so on.

The memory 220 may be a nonvolatile memory, for example an EEPROM(Electrically Erasable Programmable Read-Only Memory). The use of theEEPROM enables the information stored in the memory 220 to be stored ina stable manner for a prolonged period even without power supply andallows a user to repeatedly rewrite the stored information. In addition,in a system incorporating an EEPROM, the information in the stored inthe EEPROM may be edited.

The timing controller 210 may receive the video signal VIDEO, the audiodata signal AUDIO, and/or the control signals thereof, e.g., the videocontrol signal CON_V and/or the audio control signal CON_A, through thefirst connector 230, and may output a video data voltage, an audio datavoltage, and so on. When the timing controller 210 transmits a videodata voltage to the data driver DIC and the gate driver, an image may bedisplayed on the liquid crystal panel 100 by the data driver DIC and thegate driver.

The timing controller 210 may interface with host device 10 through thetransmission cable 240 including the bi-directional channel 320 and theone-way channel 310. In an embodiment, the timing controller 210 maytransmit the EDID through the bi-directional channel 320 of thetransmission cable 240. During this time, a HDCP (High-bandwidth DigitalContent Protection) signal may also be transmitted to the host device10. In addition, the timing controller 210 may receive control signalsfor controlling the output of the video signal VIDEO and/or the audiosignal AUDIO from the host device 10 through the bi-directional channel320 of the transmission cable 240. In an embodiment, the EDID, the HDCPsignal, and the control signals for controlling the output of the videosignal VIDEO and/or the audio signal AUDIO may belong to a monitorcontrol command set (‘MCCS’) standardized by the Video ElectronicsStandards Association (‘VESA’). The timing controller 210 may receivethe video signal VIDEO and/or the audio signal AUDIO from the hostdevice 10 through the one-way channel 310.

The timing controller 210 may be connected to the memory 220 to receivethe driving signal generation data and the EDID. As described above, thedriving signal generation data and the EDID may be transmitted from thememory 220 to the timing controller 210 through one single interface270. The interface 270 between the memory 220 and the timing controller210 may be, for example, an I2C (Inter-Integrated Circuit). The I2C mayuse an interface specification which may include only two lines of aclock signal line SCL and a data line SDA, for example as set forth inan interface specification developed by Phillips Corp. Data transmissionof the driving signal generation data and the EDID between the timingcontroller 210 and the memory 220 will later be described with referenceto FIGS. 4 and 5.

In an embodiment, the internal modules 510, 520, 530, and 540 mayinclude the power supply module 520, the inverter 510, the handlingmodule 530, and the mode display module 540.

The power supply module 520 may be connected to the second connector250, may receive an external voltage, and may generate a power supplyvoltage Vcc and supply the generated power supply voltage Vcc to theprinted circuit board 260 through the second connector 250. That is tosay, the power supply module 520 may supply the power supply voltage Vccto the memory 220, the timing controller 210, the data driver DIC andother ICs mounted on the printed circuit board 260 through the secondconnector 250.

In an embodiment, the power supply module 520 may be connected to thetiming controller 210 through the second connector 250. For example, thetiming controller 210 may supply a power saving mode signal PSM to thepower supply module 520 through the second connector 250. A power savingmode signal PSM may be a signal for interrupting the power supplyvoltage Vcc from being supplied to the backlight unit 600 to reducepower consumption. When the power supply module 520 receives the powersaving mode signal PSM, the power supply voltage Vcc may not be suppliedto the backlight unit 600.

The inverter 510 may be connected to the second connector 250 to then beconnected to the timing controller 210. For example, the inverter 510may receive a backlight on/off signal ON/OFF and a dimming signal DIMfrom the timing controller 210 and may control the on/off and luminanceof the backlight unit 600.

The handling module 530 may be connected to the second connector 250 tothen be connected to the timing controller 210. For example, thehandling module 530 may be provided in front of the liquid crystaldisplay 201 in the form of a button, as shown in FIG. 2, and maygenerate a user command signal UCS in response to user's handling. Theuser command signal UCS may be supplied to the timing controller 210through the second connector 250. The timing controller 210 may convertthe user command signal UCS into, for example, the backlight on/offsignal ON/OFF or the dimming signal DIM, to the inverter 510 through thesecond connector 250.

In an embodiment, the mode display module 540 may be connected to thesecond connector 250 to then be connected to the timing controller 210.For example, the power saving mode signal PSM output from the timingcontroller 210 may be received through the second connector 250 toindicate whether the liquid crystal display 201 is in a power savingmode.

In an embodiment, the liquid crystal display 201 may further include atransmission cable 240. The transmission cable 240 may be connected tothe first connector 230, and may include a main link transmitting videosignal and/or audio signal and an auxiliary channel transmitting controlsignals. The transmission cable 240 will be described in more detailwith reference to FIG. 3.

In an embodiment, the transmission cable 240 may be connected to thefirst connector 230 to connect the liquid crystal display 201 and thehost device 10. The transmission cable 240 may include an auxiliarychannel AUX, which may be a bi-directional channel, and a main link,which may be a one-way channel, for example including ML_Lane0,ML_Lane1, ML_Lane2, and ML_Lane3, as shown in FIG. 3. For example, thetransmission cable 240 may include a pair of auxiliary channels AUX, andfour pairs of main links ML_Lane0, ML_Lane1, ML_Lane2 and ML_Lane3. Inaddition, the transmission cable 240 may further include a hot plugdetect line HPDL, and an auxiliary power line AUX_PWR. Here, thetransmission cable 240 may be a, for example, a cable used in theDisplayPort interfacing format.

The main links ML_Lane0, ML_Lane1, ML_Lane2, and ML_Lane3 may transmitthe video signal VIDEO and/or the audio signal AUDIO received from thehost device 100 to the liquid crystal display 201. The auxiliarychannels AUX may transmit the EDID and/or the HDCP (High-bandwidthDigital Content Protection) signal received from the liquid crystaldisplay 200 to the host device 10. In addition, the auxiliary channelsAUX may transmit the control signals for controlling the output of thevideo signal VIDEO and/or the audio signal AUDIO received from the hostdevice 10 to the liquid crystal display 201. The hot plug detect lineHPDL and the auxiliary power line AUX_PWR may be channels for the liquidcrystal display 201 to interface with the host device 10 in theDisplayPort interfacing format.

In summary, the timing controller 210 may receive the EDID from thememory 220 in which the driving signal generation data and the EDID arestored, and may transmit the EDID to the host device 100 through theauxiliary channels AUX. The EDID may be received at a time oftransmitting the driving signal generation data, which may not overlap atime of transmitting the EDID. The host device 100 may transmit a videosignal, an audio signal, and/or control signals to the liquid crystaldisplay 200 through the main links ML_Lane0, ML_Lane1, ML_Lane2, andML_Lane3.

Referring to FIGS. 4 and 5, the timing controller 210 may include afirst communication module 211 and a second communication module 212.The first communication module 211 may receive the EDID and output theEDID to the outside. The second communication module 212 may receivedriving signal generation data and may output a timing controller startsignal TCON_START for starting the operation of the timing controller210.

In an embodiment, the first communication module 211 and the secondcommunication module 212 may be connected to the memory 220 through aclock signal line SCL and a data line SDA. In other words, the firstcommunication module 211 and the second communication module 212 mayreceive the EDID or the driving signal generation data from the memory220 and the I2C interface. That is to say, the first communicationmodule 211 and the second communication module 212 may receive datathrough one single interface 270. The memory 220 may therefore be sharedby the first communication module 211 and the second communicationmodule 212.

However, the time in which the first communication module 211 getsaccess to the memory 220 to receive the EDID may be made to avoidoverlap with the time in which the second communication module 212 getsaccess to the memory 220 to receive the driving signal generation data,thereby facilitating data transmission between the first communicationmodule 211/the second communication module 212 and the memory 220.

For example, the timing controller 210 may receive the EDID afterreceiving the driving signal generation data. As shown in FIG. 5, when apower supply voltage is applied to the timing controller 210, that is,the timing controller 210 is turned ON, so that the transmission cable240 is connected to the timing controller 210, the first communicationmodule 211 may output a first ready signal READY_1. For example, thefirst ready signal READY_1 may change from a first level (e.g., a lowlevel) to a second level (e.g., a high level) (t0).

In an embodiment, the second communication module 212 may get access tothe memory 220 in response to the first ready signal READY_1 and mayreceive the driving signal generation data from the memory 220. Whenreception of the driving signal generation data is complete, the secondcommunication module 212 may change the level of the first done signalDONE_1 from a first level to a second level to then deliver the firstdone signal DONE_1. In addition, the, second communication module 212may deliver a second ready signal READY_2 (t1)

The first communication module 211 may get access to the memory 220 inresponse to the second ready signal READY_2 of the second communicationmodule 212 and may receive the EDID from the memory 220. The firstcommunication module 211 having the EDID may transmit the EDID to theoutside through a bi-directional channel, for example, an auxiliarychannel AUX.

As described above, in a case where the timing controller 210 and thehost device 100 exchange various signals in a DisplayPort interfacingformat, the first communication module 211 may function as a DisplayPortreceiver. Although not shown, the host device 100 may include aDisplayPort transmitter corresponding to the DisplayPort receiver. TheDisplayPort receiver and the DisplayPort transmitter may receive andtransmit data through the main links ML_Lane0, ML_Lane1, ML_Lane2, andML_Lane3, respectively. Each of the DisplayPort receiver and theDisplayPort transmitter may include a transceiver circuit for theauxiliary channel AUX, for example a bi-directional channel. In anembodiment, the auxiliary channel AUX may be a half-duplex communicationchannel.

If the transmission of the EDID from the memory 220 to the firstcommunication module 211 is complete and an acknowledgement signal forthe EDID transmission from the outside has been received, the firstcommunication module 211 may receive a second done signal DONE_2. Thesecond communication module 212 may output a timing controller startsignal TCON_START in response to the second done signal DONE_2 which maymake the timing controller 210 initiate generation of a driving signal(t3). In other words, the timing controller start signal TCON_START maybe output in response to transitions of both the first done signalDONE_1 and the second done signal DONE_2 to the second level (e.g., highlevel).

In summary, when a power supply voltage is applied to the timingcontroller 210, so that the bi-directional channel 320 is connected tothe timing controller 210, the first communication module 211 may outputthe first ready signal READY_1, the second communication module 212 mayreceive the driving signal generation data from the memory 220 inresponse to the first ready signal READY_1 to then deliver the firstdone signal DONE_1 and the second ready signal READY_2. The firstcommunication module 211 may receive the EDID from the memory 220 inresponse to the second ready signal READY_2 to then output the EDID tothe outside. Thereafter, the first communication module 211 may outputthe second done signal DONE_2. The second communication module 212 maythen output the timing controller start signal TCON_START in response tothe second done signal DONE_2 to make the timing controller 210 start adriving signal generation process.

One or more embodiments of a liquid crystal display and a display systemincluding the same is described below with reference to FIGS. 6 and 7.FIG. 6 is a block diagram showing an exemplary liquid crystal displayand a display system including the same in accordance with anembodiment. FIG. 7 is a timing diagram illustrating operation ofmemories of first and second communication modules shown in FIG. 6 inaccordance with an embodiment.

In an embodiment, a first communication module 215 and a secondcommunication module 216 may deliver a first done signal and a seconddone signal, respectively. One or more embodiments are described belowwith regard to the differences between these embodiments and otherembodiments previously described above. The description of elementshaving the same functions or substantially the same functions may bemade briefly or omitted.

Referring to FIGS. 6 and 7, the first communication module 215 and thesecond communication module 216 may receive the driving signalgeneration data and the EDID through the memory 220 and one singleinterface 271. The first communication module 215 and the secondcommunication module 216 may be connected to the memory 220 through theclock signal line SCL and the data line SDA, respectively. As describedabove, the memory 220 may be shared by the first communication module215 and the second communication module 216, and the EDID and thedriving signal generation data may be received through an I2C interface.

In addition, the first communication module 215 and the secondcommunication module 216 may receive the EDID and the driving signalgeneration data, respectively, at different times. For example, afterthe first communication module 215 receives the EDID, the secondcommunication module 216 may receive driving signal generation data fromthe memory 220.

As shown in FIG. 7, when a power supply voltage is applied to the timingcontroller 210, that is, the timing controller 210 is turned ON, so thatthe transmission cable 240 is connected to the timing controller 210,the first communication module 215 may get access to the memory 220 IDand may start receiving EDID from the memory 220 (t0). The firstcommunication module 215 having the EDID may start transmitting the EDIDto the host device 100 to the outside through, for example, abi-directional channel 320. In an embodiment, the first communicationmodule 215 may transmit the EDID to the host device 100 in a DisplayPortinterfacing format.

If the first communication module 215 completes the transmission of theEDID, the first communication module 215 may output a first done signalDONE_1 in response to an externally applied acknowledge signal for theEDID transmission (t1). The second communication module 212 may getsaccess to the memory 220 in response to the first done signal DONE_1 tothen receive driving signal generation data from the memory 220. If thereceiving of the driving signal generation data is complete, the secondcommunication module 216 may output a second done signal DONE_2 (t2). Inan embodiment, the second communication module 216 may also output atiming controller start signal TCON_START which may make the timingcontroller 210 start generation of driving signals.

In summary, when a power supply voltage is applied to the timingcontroller 210, that is, the timing controller 210 is turned ON, so thata one-way channel 310 and a bi-directional channel 320 are connected tothe timing controller 210, the first communication module 215 mayreceive EDID from the memory 220, may transmit the EDID to the outside,and may output a first done signal DONE_1. The second communicationmodule 216 may receive driving signal generation data from the memory220 in response to the first done signal DONE_1, may output second donesignal DONE_2, and may output a timing controller start signalTCON_START in response to the first done signal DONE_1 and the seconddone signal DONE_2.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present disclosure as defined by the following claims. It istherefore desired that the present embodiments be considered in allrespects as illustrative and not restrictive, reference being made tothe appended claims rather than the foregoing description to indicatethe scope of the invention.

1. A liquid crystal display comprising: a bi-directional channel; amemory in which driving signal generation data including informationrequired to generate a plurality of driving signals and EDID (ExtendedDisplay Identification Data) are stored; and a timing controller whichreceives the driving signal generation data and the EDID from the memoryand transmits the EDID to the outside through the bi-directionalchannel, wherein the driving signal generation data and the EDID aretransmitted from the memory to the timing controller via a singleinterface, and a first time period during which the driving signalgeneration data is transmitted does not overlap with a second timeperiod during which the EDID is transmitted.
 2. The liquid crystaldisplay of claim 1, wherein the timing controller transmits the EDID ina DisplayPort interfacing format.
 3. The liquid crystal display of claim2, wherein the timing controller includes a first communication modulereceiving the EDID and outputting the EDID to the outside, and a secondcommunication module receiving driving signal generation data andoutputting a timing controller start signal for starting the operationof the timing controller.
 4. The liquid crystal display of claim 3,wherein the timing controller receives the driving signal generationdata and then receives the EDID.
 5. The liquid crystal display of claim4, wherein if a power supply voltage is applied to the timing controllerso that the bi-directional channel is connected to the timingcontroller, the first communication module outputs a first ready signal,and the second communication module, in response to the first readysignal, receives from the memory the driving signal generation data andoutputs a first done signal and a second ready signal, the firstcommunication module receiving the EDID from the memory in response tothe second ready signal.
 6. The liquid crystal display of claim 5,wherein the first communication module outputs the EDID to the outsideprior to outputting a second done signal, and the second communicationmodule outputs the timing controller start signal in response to thesecond done signal.
 7. The liquid crystal display of claim 3, wherein inthe timing controller, after the first communication receives the EDID,the second communication module receives the driving signal generationdata from the memory.
 8. The liquid crystal display of claim 7, whereinif a power supply voltage is applied to the timing controller so thatthe one-way channel and the bi-directional channel are connected to thetiming controller, the first communication module receives the EDID fromthe memory, transmits the EDID to the outside through the bi-directionalchannel, and outputs a first ready signal; and wherein the secondcommunication module, in response to the first ready signal, receivesfrom the memory the driving signal generation data, outputs a seconddone signal, and outputs, in response to a first done signal and thesecond done signal, a timing controller start signal.
 9. The liquidcrystal display of claim 1, wherein the memory is an EEPROM(Electrically Erasable Programmable Read-Only Memory).
 10. The liquidcrystal display of claim 1, wherein the interface between the memory andthe timing controller is an I2C (Inter-Integrated Circuit).
 11. Theliquid crystal display of claim 1, further comprising a one-way channelproviding one of a video signal and an audio signal, or a combinationthereof.
 12. A display system comprising: a bi-directional channel; amemory in which driving signal generation data for generating aplurality of control signals and EDID (Extended Display IdentificationData) are stored; a liquid crystal display including a timing controllerwhich receives the driving signal generation data and the EDID from thememory and transmits the EDID to the outside through the bi-directionalchannel, wherein the driving signal generation data and the EDID aretransmitted from the memory to the timing controller via a singleinterface, and a first time period during which the driving signalgeneration data is transmitted does not overlap with a second timeperiod during which the EDID is transmitted; and a host device receivingthe EDID from the liquid crystal display.
 13. The display system ofclaim 12, further comprising a transmission cable connected between theliquid crystal display and the host device, wherein the liquid crystaldisplay transmits the EDID through the transmission cable in aDisplayPort interfacing format.
 14. The display system of claim 13,wherein the liquid crystal display includes a first communicationmodule, and the transmission cable includes an auxiliary channel as abi-directional channel, and a main link as a one-way channel, the firstcommunication module transmitting the EDID to the host device throughthe auxiliary channel, and the host device transmitting one of a videosignal and an audio signal, or a combination thereof to the liquidcrystal display through the main link.
 15. The display system of claim12, wherein the timing controller includes a first communication modulereceiving the EDID and outputting the EDID to the outside, and a secondcommunication module receiving driving signal generation data andoutputting a timing controller start signal for starting operation ofthe timing controller.
 16. The display system of claim 15, wherein if apower supply voltage is applied to the timing controller so that thebi-directional channel is connected to the timing controller, the firstcommunication module outputs a first ready signal; the secondcommunication module, in response to the first ready signal, receivesfrom the memory the driving signal generation data, and outputs a firstdone signal and a second ready signal; the first communication modulereceives the EDID from the memory in response to the second readysignal; the first communication module outputs the EDID to the outsidefirst, prior to outputting a second done signal; and the secondcommunication module outputs the timing controller start signal inresponse to the second done signal.
 17. The display system of claim 15,wherein if a power supply voltage is applied to the timing controller sothat the bi-directional channel is connected to the timing controller,the first communication module receives the EDID from the memory,transmits the EDID to the outside through the bi-directional channel andoutputs a first ready signal; and the second communication module, inresponse to a first done signal, receives from the memory the drivingsignal generation data, outputs a second done signal, and outputs, inresponse to the first and second done signals, a timing controller startsignal.
 18. The display system of claim 12, wherein the liquid crystaldisplay receives one of a video signal and an audio signal, or acombination thereof from the host device.
 19. The display system ofclaim 12, wherein the memory is an EEPROM (Electrically ErasableProgrammable Read-Only Memory).